1. Field of the Invention
The present invention relates to a fast pre-charge circuit and method of providing a fast pre-charge for an integrated circuit memory device.
2. Description of the Related Art
In recent years, the size of integrated circuit devices continues to decrease resulting in considerable increase of the packing densities for these devices. The performance of the integrated circuit devices also improves as a result while the manufacture costs have gone down as well.
However, the performance of denser integrated circuit devices could drop when smaller process parameters are used. Accordingly, the issue of maintaining or controlling the precision of contact windows is particularly important as the density of integrated circuit devices continues to increase for future generations of these devices. This etching control issue is even more critical for integrated circuit devices with multiple polysilicon layers. Therefore, a so-called self-aligned contact (SAC) process which can reduce contact area is developed to deal with this issue.
Referring now to FIG. 1, there is shown a block diagram of a portion of an integrated circuit memory device. The integrated circuit memory device 100 typically includes at least a memory controller, and a plurality of memory banks. Each of the memory banks has wordlines or rows (R1, R2, . . . Rn) and bitlines or columns (C1, C2, . . . Cn). A local pre-charge control unit 102 incorporated with a wordline control 140 and a bitline control 130 is used to control the read/write of the memory cells. Typically, the wordline control 140 controls the active and de-active operations of each row of the memory array, while the bitline control 130 controls the read, write and equalize operations of each column to the memory array.
Before the activation of a wordline and accessing of the memory array, the precharge circuit charges all bitlines to a predetermined potential. Further, each bitline is shorted or equalized so that the bitlines are at an equal potential. The time required to precharge and equalize is often referred to as the precharge time or precharge period.
Referring now to FIG. 2, during the precharge stage, the potential of the wordline is also raised to a read wordline potential, typically the supply voltage VDD of the integrated circuit, or a higher voltage generated by charge pumps.
The conventional pre-charge circuit described above is affected by some problems.
One of the problems of the conventional pre-charge circuit depends on the electrical load offered by the wordlines. As shown in FIG. 2, each wordline is driven by a wordline drive power and can have a loading divided by several sections (1, 2, . . . N) of loading. In the conventional wordline or bitline driver design, a constant driving voltage is provided by the wordline or bitline power driver through the whole wordline loading. Since wordline is made of polysilicon which has a higher resistance than the metal bitline, the poly wordline transient speed is especially low.
Therefore, in a high speed memory design, less wordline loading per one wordline driving circuit is often employed in often employed in order to solve the above mentioned problem. However, if one wordline driving circuit drives less wordline loading, then the memory will have to increase the number of the wordline driving circuits, causing the memory chip size and manufacturing cost to increase.
Therefore, there is still a need for a cost effective high speed precharge circuit which can effectively solve the above-mentioned problems of the prior art.